My sons won’t stop saying “six seven”. It’s maddening. It’s not like they say it 6 or 7 times a day — peak rates are closer to 67 “six-sevens” per minute. It’s driving me crazy. They say I’m exaggerating, so I want to prove them wrong.

As proper sons of an FPGA developer, they speak in a binary stream, with each digit encoded in 4 bits (they only know how to count up to F — cute little creatures). So, 6 is 0110 and 7 is 0111.

Please design a module that receives:

a clock signal clk
a serial input bit stream brainrot

and produces:

an 8-bit unsigned output counter : out unsigned(7 downto 0)

The counter must increment by 1 each time the pattern six-seven (6→7) is detected. However, my children sometimes invert it, so you must also count seven-six (7→6).

Do not count:

six-six (6→6)
seven-seven (7→7)

Additionally, overlapping patterns must only be counted once. For example:

the sequence six-seven-six should count as one occurrence, not two.

Assume the input stream is continuous and digits are received serially, 4 bits per digit.

Try to make your design elegant.